Abstract
In this thesis, a 60-Gb/s transmitter has been implemented in 65-nm CMOS technology, which consists of a 4 x 15-Gb/s 27-1 pseudo random binary sequence (PRBS) generator, a 30-GHz phase-lock-loop (PLL), and a 4-to-1 multiplexer (MUX). The 4 x 15-Gb/s 27-1 PRBS generator can provide four parallel 15-Gb/s data for multiplexers, so no pattern generator is needed when testing the chip. The following is a 30-GHz PLL, consists of a differential voltage-controlled oscillator (VCO), a divider chain with total modulus of 64, a phase and frequency detector, and a third-order loop filter. The phase and frequency detector is based on SSB mixers and with low-pass filters to suppress the reference feedthrough . The last part of the transmitter is a 4-to-1 MUX. This 4-to-1 MUX is extension of 2-to-1 MUX by using two 30-Gb/s 2-to-1 MUXs and a 60-Gb/s 2-to-1 MUX. The 60-Gb/s 2-to-1 MUX consists of a 60-Gb/s 2:1 select circuit and 30-Gb/s input retimers. To enable to operating at 60-Gb/s, the 60-Gb/s 2:1 select circuit is based on distributed amplifiers (DA) to produce the 60-Gb/s data signal. This circuit occupies 2.1 × 1 mm2, and consumes 900 mW from a 1.5-V supply.
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