65-nm CMOS 공정을 이용한 V-Band 차동 저잡음 증폭기 설계

Abstract

In this paper, V-band differential low noise amplifier(LNA) using 65-nm CMOS process for high speed wireless data communication is presented. The LNA is composed of 3-stage common-source differential amplifiers with neutralization of feedback capacitances using MOS capacitors and impedance matching utilizing transformers. The fabricated LNA has a peak gain of 23 dB at 63 GHz and 3 dB bandwidth of 6 GHz. The chip area of LNA is 0.3 mm2 and the LNA consumes 32 mW DC power from 1.2 V supply voltage.