Abstract
This chapter deals with the case study regarding the design of a pipelined multiplier accumulator (MAC) for a stream of complex numbers. Many digital signal–processing algorithms, such as digital demodulation, filtering, and equalization, make use of MACs. A complex MAC operates on two sequences of complex numbers, {x i } and {y i }. The MAC multiplies corresponding elements of the sequences and accumulates the sum of the products. MAC calculates the result by taking successive pairs of complex numbers, one each from the two input sequences, forming their complex product and adding it to an accumulator register. The accumulator is initially cleared to zero and is reset after each pair of sequences gets processed. Since the operations must be performed in this order, the time taken to complete the processing of one pair of inputs is the sum of the delays for the three steps. One can avoid the delay by pipelining the MAC, which is, organizing it like an assembly line. Initializing and restarting the pipeline is needed to accumulate sums of products of a number of input sequences one after another. To represent the data, a 16-bit, two's-complements and a fixed-point binary representation is used. The first implementation of the MAC is a behavioral model, which allows focusing on the algorithm without being distracted by other details at the early stage of the design. Register–transfer–level model is based on the pipeline diagram.
Published Version
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