Abstract
A low power area efficient 5 bit current steering DAC is presented. The proposed DAC is integrated to prototype the readout channel for muon chamber in CBM experiment. DAC was implemented with an area of 0.019 mm2 in the CMOS process using UMS MMRF 180 nm technology. This DAC has ultralow power consumption - 25μW. The measured differential nonlinearity (DNL) is better than 0.25 LSB, integral nonlinearity (INL) is better than 0.2 LSB. In this paper the main steps of design flow, simulation results and measurement results are presented.
Full Text
Published Version (
Free)
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call