5–20 Gbit/s adaptive CTLE with spectrum balancing method

Abstract

An adaptive continuous-time linear equaliser using the optimised spectrum balancing (SB) method is proposed. The SB method is extended with a frequency detector to promote compensation ability of an equaliser and completes the optimal equalisation decision for multi-data rates. The active inductor peaking technology is adopted to increase the bandwidth of an equaliser, save chip area and power consumption. Based on Huaili Microelectronics Corporation (HLMC) 40 nm CMOS process to achieve the overall design, the power consumption and chip area are 32.11 mW at 20 Gbit/s and 0.14 mm2, respectively. And it can offer a compensation range from 6 to 18 dB for 5–20 Gbit/s of receiving data.