4H-SiC Trench MOSFET With Floating/Grounded Junction Barrier-controlled Gate Structure

Abstract

A novel silicon carbide (SiC) trench MOSFET with floating/grounded junction barrier-controlled gate structure (FJB-MOS/GJB-MOS) is presented and investigated utilizing Sentaurus TCAD simulations. The split P+ region introduced beneath the trench could better shield the gate oxide from the high electric field in the blocking mode, leading to an enhancement in the breakdown voltage while without significant degradation of other characteristics. As a result, the FJB-MOS with floating P+ shielding exhibits a higher figure of merit related to the breakdown voltage and the specific on-resistance ( ${V}_{\textsf {BR}}^{{\,\textsf {2}}}/{R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ ), which is improved by 15% and 49%, respectively, with comparison to those of the state-of-the-art double-trench MOSFET and L-shaped gate trench MOSFET. In terms of the GJB-MOS with grounded P+ shielding, it shows great advantage in reducing the switching losses thanks to the lower specific gate–drain charge ${Q}_{{\:\textsf {gd,sp}}}$ and is more conductive to high frequency applications. Additionally, the formation of the P+ region is aided by the Sentaurus Process and the processing implementation of the proposed structure is discussed.