4H-SiC DMOSFETs의 계면 전하 밀도에 따른 스위칭 특성 분석

Abstract

SiC power device possesses attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation. In general, device design has a significant effect on the switching characteristics. In this work, we report the effect of the interface states (<TEX>$Q_f$</TEX>) on the transient characteristics of SiC DMOSFETs. The key design parameters for SiC DMOSFETs have been optimized by using a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. When the <TEX>$SiO_2$</TEX>/SiC interface charge decreases, power losses and switching time also decrease, primarily due to the lowered channel mobilities. High density interface states can result in increased carrier trapping, or more recombination centers or scattering sites. Therefore, the quality of <TEX>$SiO_2$</TEX>/SiC interfaces has a important effect on both the static and transient properties of SiC MOSFET devices.