4-bit multiplexer/demultiplexer chip set for 40-Gbit/s optical communication systems

K Ishii,T Shibata,H Nosaka,K Kurishima,E Sano,M Ida,T Enoki,S Yamahata

doi:10.1109/rfic.2003.1213894

4-bit multiplexer/demultiplexer chip set for 40-Gbit/s optical communication systems

K Ishii, T Shibata + Show 6 more

https://doi.org/10.1109/rfic.2003.1213894

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Publication Date: Jun 8, 2003

Citations: 4

Affiliation: NTT (Japan), Hokkaido University

#Clock And Data Recovery #Demultiplexer + Show 8 more

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Abstract

We have designed and fabricated a low-power 4:1 multiplexer (MUX), a 1:4 demultiplexer (DEMUX), and a 1:4 DEMUX with a clock and data recovery (CDR) circuit using undoped-emitter InP/InGaAs heterojunction bipolar transistors (HBTs). Our HBTs exhibit an f/sub T/ of about 150 GHz and an f/sub max/ of about 200 GHz at a collector current density of 50 kA//spl mu/m/sup 2/ and a collector-to-emitter voltage of 1.2 V. Error-free operations at bit rates of up to 50 Gbit/s have been confirmed for the 4:1 MUX and 1:4 DEMUX, which dissipate 2.5 W and 2.6 W, respectively. In addition, 40-Gbit/s error-free operation for the full clock rate 1:4 DEMUX with the CDR has been achieved for the first time.

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