4-bit adder-accumulator at 41-GHz clock frequency in InP DHBT technology

Abstract

A 41-GHz 4-b adder-accumulator test circuit implemented in InP double heterojunction bipolar transistor (DHBT) technology using 624 transistors is reported. High clock rates are obtained by combining the logic functions into pipelined latches. The adder-accumulator contains a single-level parallel-gated carry circuit that is used as a step toward reduced power consumption. The carry circuit has a maximum clock frequency of 55 GHz. The accumulator architecture employs modular, pipelined 2-b adders and is cascadable to 2 N-bits. The test circuit includes a 4-b digital to analog converter (DAC) that facilitates demonstration of high-speed operation.