4768193 Semiconductor memory device having error correction function and incorporating redundancy configuration

Abstract

A semiconductor memory device having a main memory cell array including a plurality of rows of cell arrays, each row corresponds to a two-dimensional virtual matrix configuration. A redundancy memory cell array is provided which includes a plurality of rows of redundancy memory cells, each row corresponding to one horizontal or vertical group of memory cells of the virtual matrix configuration. When a selected memory cell is a predetermined defective cell, a row of memory cells including the defective cell is replaced with the redundancy memory cell array, thereby correcting a hard error. Also, the defective cell is accessed by an error checking and correcting circuit of a horizontal and vertical parity checking type. A horizontal or vertical group of memory cells including the selected memory cell is replaced with the corresponding row of the redundancy memory cell array, thereby correcting a soft error and a hard error other than the predetermined hard error.