Abstract
This paper presents an in-depth study of a 45-nm CMOS silicon-on-insulator (SOI) technology. Several transistor test cells are characterized and the effect of finger width, gate contact, and gate poly pitch on transistor performance is analyzed. The measured peak ft is 264 GHz for a 30 × 1007 nm single-gate contact relaxed-pitch transistor and the best fmax of 283 GHz is achieved by a 58 × 513 nm single-gate contact regular pitch transistor. The measured transistor performance agrees well with the simulations including R/C extraction up to the top metal layer. Passive components are also characterized and their performance is predicted accurately with design kit models and electromagnetic simulations. Low-noise amplifiers from Q- to W-band are developed in this technology and they achieve state-of-the-art noise-figure values.
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