Abstract
Apparatus for testing dynamic noise immunity of digital integrated circuits wherein noise pulses of prefixed duration and amplitude are applied to the inputs of an integrated circuit under test. The tested circuit outputs which normally are at logic level 0 are connected to the inputs of a first group (6) of control logic gates, whilst the tested circuit outputs which normally are at logic level 1 are connected to the inputs of a second group (7) of control logic gates. The outputs of such groups feed a fault detection circuit (10). The input voltage thresholds of control logic gates is adjusted by suitable circuits (8, 9) so as to check the dynamic noise immunity of the integrated circuit under test for a prefixed logic swing.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
