3-State behavior in quantum dot gate FETs

Abstract

Quantum dot (QD) gate Si FETs, exhibiting an intermediate state “i” in their transfer characteristics, were first reported in ISDRS-07 [1]. The “i” state is characterized by a low-current saturation behavior which occurs in a range of gate voltage. Its origin is attributed to the transfer of charge from the inversion channel to the either one of the two cladded quantum dot (e.g. SiO x -Si) layers assembled in the gate region over the thin gate insulator [1,2]. The tunneling of charge from the inversion layer to the first layer of Si quantum dots (and their eventual transfer to the second layer of Si quantum dots via resonant tunneling as the gate voltage is increased) results in an increase the threshold voltage. The variation of the threshold voltage due to compensation of the gate insulator charge results in a low current saturation “i” state.