Abstract
The advent of powerful microprocessors that surpass our number-crunching requirements has not relieved the need of HEP experimenters to design and build ASICs for front-end and triggering applications, because a simpler and specialized circuit is still required. One such circuit is the 3D-Flow processor which is almost equivalent in number of gates to the glue logic alone required in a powerful microprocessor system. Better described as an architecture rather than merely an ASIC, the 3D-Flow allows the user to build a programmable Level-1 trigger, and it is also suitable to be used in data acquisition (DAQ), data movement, pattern recognition, data coding and reduction. Test vectors, including several Level-1 trigger and DAQ algorithms, have been generated for the 3D-Flow ASIC. Pattern recognition algorithms for
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