3D Thermal Stress Models for Single Chip SiC Power Sub-Modules

Abstract

ABSTRACTThree dimensional models of single chip SiC power sub-modules were generated using ANSYS in order to simulate the effects of various substrate materials, heat fluxes, and heat transfer coefficients on temperature and thermal stress contours. Silicon nitride, aluminum-nitride, alumina were compared as substrates with or without an additional layer of CVD diamond on either top or bottom of the surfaces. Simulated heat fluxes of 100 to 300 watts/cm2 resulted in device junction temperatures in the range of 377 to 535 K. With modest cooling, represented by a heat transfer coefficient (hconv) of 3350 watts/m2 K, SiC chips operated at 300 watts/cm2 power density maintained junction temperatures Tj < 535 K. Both the maximum and minimum chip temperature decreased with increasing heat transfer coefficient from 50 to 5000 watts/m2 K. In the applied heat flux range, the minimum and maximum Von Mises stress of a simulated single SiC device sub-module was between 946 MPa to 1.31GPa. If consistent with simulation results, CVD diamond integrated substrates should be superior to those comprised of only AlN, Al2O3, and Si3N4. Experimental validation of ANSYS results and more extensive multiple-chip power module simulations will also be explored.