3D Thermal Stress Model for SiC Power Modules

Abstract

Three dimensional models of both single-chip and multiple-chip power sub-modules were generated using ANSYS in order to simulate the effects of various substrate materials, heat fluxes, heat transfer coefficients, and device placement configurations on temperature and thermal stress contours. Alumina, aluminum-nitride, and CVD diamond were compared as substrates. Heat fluxes of 100 to 500 watts/cm2 resulted in SiC device junction temperatures in the range of 350 to 650 K. The predicted maximum operating temperature for a chip, to which 300 watts/cm2 of heat flux was applied, would be 239°C (512 K). In the applied heat flux range, the minimum and maximum Von Mises stress of a simulated single SiC device sub-module was between 1.2 MPa to 2.4 GPa. The maximum shear stress at 300 watts/cm2 was predicted to be 243 MPa. Both the maximum and minimum chip temperature decreased with increasing heat transfer coefficient from 25 to 2500 watts/m2 K. With modest cooling, represented by a heat transfer coefficient (hconv) of 250 watts/m2 K, SiC chips operated at 300 watts/cm2 power density maintained junction temperatures Tj < 400 K. If consistent with simulation results, CVD diamond integrated substrates should be superior to those comprised of AlN or Al2O3. Asymmetric device placement in the multi-chip module proved more effective at avoiding potential hot spots than the symmetric configuration.