3D TCAD simulations of strained Si CMOS devices with silicon-based alloy stressors and stressed CESL

Abstract

Stress distributions in the Si channel regions of silicon-based alloy source/drain and stressed silicon nitride liner NMOSFETs with various widths were studied using 3D TCAD simulations. For strained Si NMOS, drive current enhancement was found to be dominated by tensile stress along the transport direction ( S xx ), and compressive stress along the growth direction ( S zz ) in larger width devices. Stress along the width ( S yy ) was found to have the least effect on the drain current in the large width regime. The compressive stress along the vertical direction, perpendicular to the gate oxide ( S zz ), contributes significantly to drive current enhancement and cannot be neglected in NMOSFETs. For strained Si PMOS, it is found that S xx contributes most substantially to the improvement in drive current, while S zz contributes the least. In the narrow width regime S yy noticeably enhances drive current, contributing almost a quarter of the total gain.