Simulation of a nanoscale strained Si NMOSFET with a silicon–carbon alloy stressor

Abstract

The stress distribution in the silicon (Si) channel regions of silicon–carbon (SiC) source/drain negative-metal-oxide semiconductor field-effect transistors (NMOSFETs) with various widths was studied using three-dimensional (3D) process simulations. The drive current enhancement in wide devices was dominated by the tensile stress along the transport and vertical directions. Stress along the width (transverse) direction has the least effect on the drain current in wide devices. Stress along the width direction in narrow devices was found to degrade the drive current gain and cannot be neglected. In addition, a reduction of device width was found to reduce the drive current gain due to the presence of less compressive stress in the vertical direction in the device channel, caused by the shrinking SiC regions. The impact of width on performance improvements such as drive current mobility gain was analyzed using Technology Computer-Aided Design (TCAD) simulations.