3D Super chip technology to achieve low-power and high-performance system-on-a chip

Abstract

A new three-dimensional (3D) integration technology based on a reconfigured wafer-to-wafer bonding method called a super-chip integration has been developed to achieve low-power and high-performance system-on-a chip (SoC). A number of known good dies (KGDs) are simultaneously aligned and bonded onto lower chips or wafers with high alignment accuracy by using a new self-assembly technique in a super-chip integration.