New Three-Dimensional Integration Technology Based on Reconfigured Wafer-on-Wafer Bonding Technique

Abstract

We have proposed a new three-dimensional (3D) integration technology based on reconfigured wafer-on-wafer bonding technique to solve several problems in 3D integration technology using the conventional wafer-on-wafer bonding technique. 3D LSIs are fabricated by bonding the reconfigured wafers onto the supporting Si wafer. The reconfigured wafer consists of many known good dies (KGDs) which are arrayed and glued on a holding Si wafer with Si steps by chip self-assembly technique. Therefore, the yield of the reconfigured wafer can be 100%. As a result, we can obtain a high production yield even after bonding many wafers. In addition, it is not necessary in the reconfigured wafer that the chip size has to be identical within the wafer. Therefore, we can stack various kinds of chips with different chip sizes, different materials and different devices in our new 3D integration technology based on the configured-wafer-on-wafer bonding technique (Reconfig. W-on-W 3D technology). We have developed key technologies to form W through-Si-Via (TSV) in the reconfigured wafer to fabricated 3D LSI test chips. We obtained excellent electrical characteristics of W-TSV using the daisy chain in 3D LSI test chip.