3D Sequential Low Temperature Top Tier Devices using Dopant Activation with Excimer Laser Anneal and Strained Silicon as Performance Boosters

Abstract

Top tier devices in a 3D sequential integration are optimized using a low temperature process flow $( . Bi-axial tensile strained silicon is transferred without strain relaxation to boost the top tier nmos device performance by 40-50% over the unstrained silicon devices, recovering the performance loss from the low temperature processing when using extension-less device integration. Excimer laser anneal is also shown to effectively activate both n-type and p-type dopants in the extension of thin silicon film devices using optimized, CMOS compatible, laser exposure conditions. Laser anneal is fully compatible with a replacement metal gate (RMG) process flow and with selective source/drain (SD) epitaxy. The dopant activation level is preserved during the entire process flow which results in similar $\mathrm{I}_{\mathrm{on}}-\mathrm{I}_{\mathrm{off}}$ device performance for devices with laser and spike anneals. Excimer laser anneal benefits also from improved control short channel effects over spike annealing due to low dopant diffusion.