Abstract
As the field of quantum computing advances from the few-qubit stage to larger-scale processors, qubit addressability and extensibility will necessitate the use of 3D integration and packaging. While 3D integration is well-developed for commercial electronics, relatively little work has been performed to determine its compatibility with high-coherence solid-state qubits. Of particular concern, qubit coherence times can be suppressed by the requisite processing steps and close proximity of another chip. In this work, we use a flip-chip process to bond a chip with superconducting flux qubits to another chip containing structures for qubit readout and control. We demonstrate that high qubit coherence (T1, T2,echo > 20 μs) is maintained in a flip-chip geometry in the presence of galvanic, capacitive, and inductive coupling between the chips.
Highlights
Superconducting qubits are a prime candidate for constructing large-scale quantum processors due to their lithographic scalability, compatibility with microwave control, gate speed, and relatively long coherence times in planar geometries.[1,2]
Recent increases in coherence times[3,4,5] and the development of fast, high-fidelity single-qubit gates[6,7,8] and two-qubit gates[7,9] have yielded control fidelities that exceed the most lenient thresholds required for fault tolerant quantum error correction via the surface code,[10] a code of particular interest because it requires only nearest-neighbor interactions between qubits
Moving into the third dimension eases such geometrical constraints, enabling efficient interconnect routing to large 2D arrays, allowing for more compact qubit-qubit coupling geometries, and affording significantly increased connectivity beyond nearest-neighbor interactions that is advantageous for many error correcting codes[10,15,16] and of importance to quantum annealing and quantum simulation
Summary
Superconducting qubits are a prime candidate for constructing large-scale quantum processors due to their lithographic scalability, compatibility with microwave control, gate speed, and relatively long coherence times in planar geometries.[1,2] Recent increases in coherence times[3,4,5] and the development of fast, high-fidelity single-qubit gates[6,7,8] and two-qubit gates[7,9] have yielded control fidelities that exceed the most lenient thresholds required for fault tolerant quantum error correction via the surface code,[10] a code of particular interest because it requires only nearest-neighbor interactions between qubits With this motivation, recent experiments have prototyped basic error-detection codes, Bell-state memories, and multi-qubit entangled states using four,[11] five,[12] nine,[13] and ten qubits[14] in a planar geometry. Moving into the third dimension eases such geometrical constraints, enabling efficient interconnect routing to large 2D arrays, allowing for more compact qubit-qubit coupling geometries, and affording significantly increased connectivity beyond nearest-neighbor interactions that is advantageous for many error correcting codes[10,15,16] and of importance to quantum annealing and quantum simulation
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