3D IC interconnect parasitic capacitance extraction with a reformulated PGD algorithm

Abstract

Proper generalized decomposition (PGD) is a new model order reduction (MOR) method based on the use of separated representations. In this work, PGD is applied on 3D capacitance extraction of interconnects in IC to reduce its computational complexity. To make the PGD solver feasible, the complex geometries are simplified by a characteristic function technique. 3D singular value decomposition (SVD) of the characteristic functions is avoided by a reformulation of the PGD algorithm. A numerical example is given to verify the method.