3-D IC Interconnect Parasitic Capacitance Extraction With a Reformulated PGD Algorithm

Abstract

Proper generalized decomposition (PGD) is a recently developed model-order reduction method based on the use of variable-separated representations. In this paper, space variable-separated PGD is applied on the 3-D capacitance extraction of interconnects in integrated circuits to reduce its computational complexity. To make the PGD solver feasible, the complex boundary conditions are simplified by a characteristic function technique. 3-D singular-value decomposition of the coefficient functions is avoided by using a reformulated PGD algorithm, and therefore, the proposed method can effectively deal with problems with inhomogeneous dielectric layers and dummy fills. Numerical examples are given to verify the method.