3D-Flow with fewer than 100 K gates versus other processors for DAQ and Level-1 trigger

Abstract

The advent of powerful microprocessors that surpass our number-crunching requirements has not relieved the need of HEP experimenters to design and build ASICs for front-end and triggering applications, because a simpler and specialized circuit is still required. One such circuit is the 3D-Flow processor. Better described as an architecture rather than merely an ASIC, the 3D-Flow allows the user to build a programmable Level-1 trigger, and it is also suitable to be used in data acquisition (DAQ), data movement, pattern recognition, data coding and reduction. Test vectors, including several Level-1 trigger and DAQ algorithms, have been generated for the 3D-Flow ASIC. Pattern recognition algorithms for a calorimeter take less than 500 ns to execute. The system also implements sophisticated tracking and trackmatching algorithms, and can execute thousands of steps in Single Instruction Multiple Data (SIMD) mode. The high degree of connectivity between processors, and their multiple operation execution capabilities, is an especially significant advantage with respect to other systems. At present the 3D-Flow system is the only detailed study demonstrating the feasibility of executing several Level-1 trigger and data reduction algorithms of different experiments.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>