3D Chip Integration with through Silicon-Vias (TSVs)

Abstract

Three-dimensional (3D) integration using through Silicon-Vias (TSVs) allows the formation of high signal bandwidth, fine pitch, and short-distance interconnections in stacked dies. There are several approaches for 3D chip stacking which includes chip to chip, chip to wafer, and wafer to wafer. Chip-to-chip integration and chip-to-wafer integration provides the ability to stack known good dies (KGD), which can lead to higher yields without integrated redundancy. In near future, with structure and process optimization, wafer-to-wafer integration may provide an ultimate solution for the highest manufacturing throughput assuming a high yield and minimal loss of good dies and wafers. In future, chip-to-chip and chip-to-wafer integration may offer high yield, high flexibility, and high performance with added time to market advantages. In this paper, 3D integration using chip to chip, chip-to-wafer & wafer to wafer approaches has been described. 3D chip integration technology and 3D stack technology with TSVs are discussed.