3D Analytical TEM Approach to Effectively Characterize 3D-FinFET Device Features in Semiconductor Wafer-foundries

Abstract

Introductions of 3-Dimentional FinFET transistors in semiconductor device open a new era for continuous shrinkage of semiconductor transistor nodes. One big challenge for physical failure analysis (PFA) and transmission electron microscopy (TEM) is that, for device of 20nm, 14nm, an beyond, features of interests (FOI) are mostly thinner than a thickness of a TEM lamella (say, around 50~150nm), depending on the orientation. This adds in ambiguity in interpretation of the TEM imaging straightforward. Combined with intrinsic complexity from the 3D-FinFET structures themselves, PFA/TEM teams at waferfoundries truly have to constantly think out of box for novel approaches to effectively and timely isolate faults and conclusively identify root-causes of yield detractors [1~4].