Abstract
We usually do Physical Failure Analysis (PFA) to visualize the failure in the semiconductor process. First, we find the site-specific target (or failed cell). And then, we should do de-processing which contains lapping and chemical etch. As the semiconductor gets more complex and multi-layer, we should do multi-de-processing steps. If the failure has the oxide-material, we cannot know the cause of failure. Because the oxide can be removed by Hydrogen Fluoride (HF) chemical, which means the failure will be gone during de-processing step. We should use Focused Ion Beam (FIB) which can make a thin sample to exclude chemical step. High-resolution analytical tools such as Transmission Electron Microscopy (TEM) have become indispensable in PFA. We make a Dual-Axis TEM (DAT) method for PFA. We make a Plan-view TEM (PTEM) sample with FIB first, we can find an exact location of failure through the first step. And then, we make cross-sectional TEM (XTEM) sample with a site-specific target in PTEM sample. Below summarizes the four major steps and its precautions;1. Making a Planar lamella by FIB2. Observing a PTEM specimen with TEM(Precaution : zone axis should be adjusted exactly)3. Making a cross-section lamella by FIB(Precaution : Protection layer should be deposited on both sides)4. Observing a XTEM specimen with TEMWe propose DAT method to improve the problem of artifact in de-processing step. The TEM result with DAT method is shown in figure 4. We can know the exact location of failure with observing a PTEM sample. We can know the cause of failure with observing a XTEM sample. Moreover, we can analysis the chemical and physical information through DAT method. This method is very effective and has a high success rate in analysis. REFERENCE [1] A.E.M. De Veirman, “3-Dimensional’ TEM silicon-device analysis by combining plan-view and FIB sample preparation”, Materials Science and Engineering: B, 102(1-3), pp. 63-69, 2003. [2] Jon C. Lee, David Su, J.H. Chuang, “A Novel Application of the FIB Lift-out Technique for 3-D TEM Analysis”, Microelectronics Reliability Asset, 41(9-11), pp. 1551-1556, 2001. Figure 1
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