Abstract
AbstractThis paper proposes a 3.4Gbps/lane intra‐panel interface with 11.1% of the protocol overhead for the raw data to be transmitted. The proposed intra‐panel interface uses a point‐to‐point interface architecture with embedded clock. To reduce the EMI radiation, the scrambling scheme was adopted. The protocol of the proposed intra‐panel interface provides a PLL based clock and data recovery (CDR) scheme for the receiver. Timing controller (TCON) and source driver (SD) are implemented using 45nm/1.1V and 0.18um/1.8V CMOS processes, respectively. The proposed interface is verified on a 55‐inch Full‐HD TFT‐LCD panel with 8bit RGB and 120‐Hz frame rates. The maximum data rate per lane was measured as up to 3.4Gbps/lane.
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