300 mm SiGe-On-Insulator Substrates with High Ge Content (70%) Fabricated Using the Smart Cut™ Technology

Abstract

Bulk silicon device technologies are reaching fundamental scaling limitations. The 28 nm and 22 nm technology nodes have seen the introduction of Ultra-Thin Body and Buried Oxide Fully Depleted SOI (UTBB-FDSOI) [1] and FinFETs [2], respectively. Fully Depleted transistor technologies are mandatory to suppress short channel effects. Today, all major research and development alliances carry the message that the silicon and its Fully Depleted transistor technologies have the potential to address roadmap requirements down to the 10 nm node. High mobility materials are expected to replace silicon as the channel material: attention has recently been focused on III-V (such as GaAs or InGaAs) and germanium (Ge). Ge has a privileged status: indeed, it belongs to column IV of Mendeleiev Table and it is a good candidate for high mobility p-channel and n-channel devices. Hole mobility (respectively electron mobility) in bulk Ge is indeed roughly 4 times (2 times) that in bulk Si. Nevertheless, changing from Si to Ge influences more than just the on-state current. The smaller bandgap value of Ge (0.66 eV versus 1.12 eV for Si) increases the junction leakage, and may therefore lead to a significant increase in the transistor off-state current [3-4]. SiGe alloy material with a high Ge ratio is a good compromise. Recently high-Ge-content (HGC) SiGeOI finFET have been demonstrated with record mobility values and good cut-off behavior [5] indicating the potential of such a channel material. In this paper, we will present our work on 300 mm SiGe-on-insulator (SiGe-OI) substrates with high Ge concentrations (70%). The process flow is illustrated in Fig.1. The standard SOI Smart CutTM process has been adapted for SiGe-OI substrates. The first focus is on the donor substrate and the SiGe epilayers. The donor surface quality should be carefully controlled and optimized before the bonding step. Fig. 2 shows the X-ray reflectivity measurements on the top layers of the Si0.3Ge0.7stack at the end of the epitaxial process steps. The significant interference fringes indicate the good quality of the different surfaces and interfaces which is confirmed by the roughness measurement (Atomic Force Microscopy image in Fig. 2 - right) with a Root Mean Square (RMS) roughness value as low as 0.18 nm on top of the donor substrates. The bonding process and the adapted Hydrogen-induced layer transfer inside the HGC SiGe layer will be presented. The second focus is on the finishing process steps to obtain the desired HGC SiGe-OI substrate. To ensure a good thickness control, the combination of multi-layer donor materials and selective chemical etching process has replaced the polishing removal process. As shown in Fig. 3, it enables to reach a SiGe-OI layer of 56 nm with a uniformity of +/- 3.5 nm at a 300 mm substrate scale. Final RMS surface roughness as low as 0.3 nm is obtained on finished HGC SiGe-OI substrate. Acknowledgment: The authors are grateful for the support given by the European Commission (ECSEL-WAYTOGO FAST 662175) [1] J. Hartmann, FDSOI workshop, 2012 [2] C. Auth, VLSI-T, 2012 [3] C. Claeys and E. Simoen, Eds., Germanium-based technologies – From materials to devices. Elsevier, 2007. [4] G. Eneman, ESSDERC 2007. [5] Hashemi, VLSI 2015. Figure 1