Highly-strained SGOI p-channel MOSFETs fabricated by applying Ge condensation technique to strained-SOI substrates

Abstract

Much attention has recently been paid to MOS channel materials with high mobility and resulting high injection velocity that can increase ION and reduce delay [1]. Among them, ultrathin body SiGe-On-Insulator (SGOI) structure with high compressive strain and high Ge content is a promising channel material for pMOSFETs under future technology nodes. Here, many theoretical studies [2–4] have reported that incorporation of a large amount of compressive strain into SiGe materials is a key technology for boosting the performance. Also, one of promising techniques for fabricating the SGOI structures is Ge condensation technique, composed of epitaxial growth of SiGe layers on SOI substrates and successive thermal oxidation [5, 6]. It is known, however, in Ge condensation using conventional unstrained SOI substrates [5, 7, 8] that strain relaxation occurs when Ge content becomes ∼0.60 and strain significantly decreases with an increase in Ge content. This strain relaxation has been attributed to crystal defect generation during Ge condensation, induced by large strain in the SGOI due to the lattice mismatch between Si and Ge [8–10].