3 - The RISC challenge

Abstract

This chapter discusses the reduced instruction set computers (RISCs) challenge. The computer giant IBM is usually acknowledged as the first company to define a RISC architecture in the 1970s. This research was further developed by the Universities of Berkeley and Stanford to give the basic architectural models. RISC can be described as a philosophy with three basic tenets: (1) all instructions will be executed in a single cycle, (2) memory will be accessed only via load and store instruction, and (3) all execution units will be hardwired with no micro-coding. Two generic RISC architectures form the basis of nearly all the current commercial processors. The main differences between them concern register sets and usage. They both have a Harvard external bus architecture consisting of separate buses for instructions and data that allows data accesses to be performed in parallel with instruction fetches and removes any instruction/data conflict. If these two streams compete for a single bus, then any data fetches stall the instruction flow and prevent the processor from achieving its single-cycle objective. Executing an instruction on every clock requires an instruction on every clock.