3-D Power Delivery Network’s Subblocks and Regulator Placement Optimized by Evolutionary Algorithm

Abstract

A performance-aware 3-D power delivery network (PDN) using a novel common-centroid regulator placement and computational intelligence is presented. An evolutionary algorithm has been employed to evaluate the optimal performance tradeoffs such as power, latency, and signal integrity and to find the best performance placement of regulators in intertier PDN. To analyze main benefits of the proposed on-chip 3-D PDN, the regulator, most important block, is presented in the PDN. Through-silicon via and I/O links are also integrated into the 3-D PDN to analyze the power noise accurately. The proposed 3-D PDN using evolutionary process can significantly improve the energy efficiency, supply noises, and power/signal quality of a heterogeneous 3-D PDN. It is designed and fabricated in a 65-nm CMOS technology at 1 V. The measurement results show that the supply voltage fluctuation is 10.2 mV and the total power consumption of the proposed 3-D PDN is 4.22 mW while the 3-D I/O transceiver operates with a data rate of 1.9 Gb/s.