Chiplet/Interposer Co-Design for Power Delivery Network Optimization in Heterogeneous 2.5-D ICs

Abstract

In this article, we present an effective methodology for co-design, co-analysis, and the system-level optimization of chiplet/interposer power delivery network (PDN) in 2.5-D integrated chip (IC) designs. In our methodology, we first generate a commercial-grade heterogeneous 2.5-D IC designs including full signal routing and power delivery. We then perform our PDN co-analysis in frequency and time domains on the entire PDN to evaluate various mechanisms added to our PDN designs. Based on our co-analysis results, we perform the system-level optimization on both interposer and chiplet PDNs with the stable performance of power delivery. Finally, we perform power, performance, and area (PPA) analysis and power integrity (PI) on our 2.5-D designs and discuss tradeoffs in chiplet and interposer levels due to PDN optimization. Our experiments show 27.17% improvement in the overall IR-drop in the optimized 2.5-D IC design by increasing the interposer PDN occupancy by 5.52% and inserting the additional PDN grids in chiplet designs. However, we also observe tradeoffs in terms of PPA and PI. By PDN optimization, the optimized design has an 11.6% increase of the total power, while the area of 2.5-D design remains the same. Moreover, from the perspective of PI, the tradeoffs are shown by 0.6% reduction of power efficiency, 32.6% higher output ripple, and 31.5% higher initial ringing because of an inductive behavior of interposer PDN in the optimized design.