3-D Integrated Chiplet Encapsulation (3-D ICE): High-Density Heterogeneous Integration Using SiO2-Reconstituted Tiers

Abstract

We propose a 3D heterogeneous integration technology called 3D Integrated Chiplet-Encapsulation (3D ICE). The proposed 3D ICE architecture encapsulates chiplets into a reconstituted tier using low-temperature (100 °C) ICP-PECVD SiO2 deposition. The SiO2-reconstituted-tier in this work is 10 μm thick with through-oxide vias that are 2 μm in diameter and 10 μm in pitch (104 /mm2 via density), which exceeds vias in conventional fan-out packaging. Tier-transferring using KOH wet-etch is also reported. Lastly, four-point Kelvin resistance measurements are performed for Cu-filled through-oxide-vias of various dimensions. The resistance of a 50 μm diameter single via is 36 mΩ and that of a 2 μm diameter via is 1.14 Ω.