Abstract
It's believed that 3D integration technology is a solution to beyond More-than-Moore law and to bring incremental cost-power-performance value. An advanced 3D dislocation multi-stack integration structure by fan-out wafer-level packaging has been developed for 3D integration. Four ultra-thin NAND Flash chips which thickness is about 40um can be integrated by Package-on-Package (PoP) method. The package size is <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">${18\text{mm}\times 12}$</tex> mm <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">${\times 0.89\text{mm}}$</tex> , and BGA pitch is 1mm. The 3D dislocation multi-stack integration technology can be used as an alternatives solution to wire bonding and through-silicon-via (TSV) technology for NAND flash packaging.
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