3.5: Optimization of LTPS‐AMOLED Array Design to Enhance the Resistance to ESD risk

Abstract

Electrostatic discharge (ESD) is a significant cause of yield loss in FPD (Flat Panel Display) array manufacturing. LTPS‐TFT Arrays processing includes a series of chucking and conveyance steps, in which, some of these steps would generate triboelectric charge [1, 2]. Although low‐impedance materials for equipment contact parts with glass substrate have been adopted, and good grounding has been implemented, ESD still happens frequently. In order to understand the root‐cause of ESD and to minimize the ESD effect, it is necessary to have a systematic research on LTPS‐TFT Arrays processing. By studying and identifying the locations of ESD in different LTPS‐AMOLED products , we found three ESD causes related to the different array designs as described below: Overlap between adjacent metal layers is easy to generate ESD, e.g. the overlap of metal 1 line of EM and metal 2 jumper line of Vdata, the overlap of metal 1 jumper line of Vdata and metal 2 jumper line of VDD, the overlap of metal 2 line of Vref and metal 1 jumper line of Vdata. Research on ESD in products’ GIP (Gate Driver in Panel) area indicates that the distance of Capacity C1/C2 in GIP‐Scan circuit, D1 for short, and the area difference of C1/C2 have an obvious correlation with ESD, in which the products’ resistance to ESD risk is enhanced with the increase of D1 distance and the decrease of C1/C1 area difference. Study of ESD in CT (Cell Test) area shows that CT ESD has a strong correlation with IC Pad, including COF Pad & IC output Pad, in which, ESD occurs easily when IC Pad is connected to CT circuit directly. By optimizing array design, products with excellent resistance to ESD risks can be obtained.