2D-Electrothermal Analysis of Device Failure in Advanced MOS Processes

Abstract

The most common protection schemes used in MOS ICs rely on the parasitic bipolar transistor associated with the nMOS devices. A basic MOS protection network includes an nMOS device whose drain is connected to the pin to be protected with the source tied to ground. The protection level or failure threshold can be set by varying the nMOS device width, provided uniform conduction is achieved. Under stress conditions, the dominant current conduction path between the protected pin and ground involves the parasitic bipolar transistor associated with the nMOS device. This parasitic bipolar transistor operates in the snapback region when the pin is stressed positive with respect to ground. Typical breakdown characteristics of a grounded-gate nMOS device are shown for reference in Fig 6.1. Generally, the nMOS protection device will fail under ESD/EOS as a result of the second breakdown which causes the current localization and the eventual device failure (thermal runaway) [87, 5]. Thermal runaway is a positive feedback process in a circuit component produced by the coupling of the device self-heating and the temperature-dependent electrical parameters under stress conditions.