Abstract
A computationally efficient algorithm called a subsequent-division algorithm is presented to develop a special-purpose VLSI processor for differential inverse kinematics computation of redundant manipulators. Because the computation is performed in a feedback loop not only the throughput but also the delay time must be considered as a performance factor. An architecture of a reconfigurable parallel VLSI processor is proposed to reduce the delay time by improvement of the ratio of the multipliers contained in the processing elements (PEs). Chip evaluation based on the 1- mu m CMOS design rule shows that the delay time for differential inverse kinematics (DIK) computation of a 12-degree-of-freedom (DOF) redundant manipulator becomes about 13 mu m, which is about 90 times faster than that of a parallel processor approach using general-purpose microprocessors. >
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
