Abstract
Carry and sum circuits for a 2-bit adder used in a pipelined 2N-bit adder-accumulator architecture are reported. To obtain high clock rates in a design with multiple gate delays a novel merged AND-OR-Latch structure using four-level series gated current steering logic is employed. These integrated circuits were fabricated in InAlAs/InGaAs transferred substrate heterojunction bipolar transistor technology and operate up to 19 GHz clock rate.
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