15‐2: A 6.0Gbps Clock Embedded Interface for Advanced Mobile Displays

Abstract

Compared to the conventional clock‐forwarded scheme (MIPI D‐PHY) for display data transmission in mobile product, we propose a high‐speed clock embedded interface for advanced mobile display driving architecture. To achieve compatibility with simple interface protocol, we suggest a perturbation‐minimized D‐PHY operation. Furthermore, we propose a novel fast wake‐up CDR architecture to mitigate the intrinsic drawback comes from clock/training overhead. We demonstrate that our massproducible system successfully operates at 6.0Gbps by using a MIPI compatible design as an example.