14‐Bit Fully Differential SAR ADC with PGA Used in Readout Circuit of CMOS Image Sensor

Abstract

This paper proposes a 14‐bit fully differential Successive Approximation Register (SAR) Analog‐to‐Digital Converter (ADC) with a programmable gain amplifier (PGA) used in the readout circuit of CMOS image sensor (CIS). SAR ADC adopts two‐step scaled‐reference voltages to realize 14‐bit conversion, aimed at reducing the scale of capacitor array and avoiding using calibration to mitigate the impact of offset and mismatch. However, the reference voltage self‐calibration algorithm is applied on the design to guarantee the precision of reference voltages, which affects the results of conversion. The three‐way PGA provides three types of gains: 3x, 4x, and 6x, and samples at the same time to get three columns of pixel signal and increase the system speed. The pixel array of the mentioned CIS is 1026 × 1024, and the pixel pitch is 12.5 μm × 12.5 μm. The prototype chip is fabricated in the 180 nm CMOS process, and both digital and analog voltages are 3.3 V. The total area of the chip is 6.25 × 18.38 mm2. At 150 kS/s sampling rate, the SNR of SAR ADC is 71.72 dB and the SFDR is 82.91 dB. What is more, the single SAR ADC consumes 477.2 uW with the 4.8 VPP differential input signal and the total power consumption of the CIS is about 613 mW.