14-bit column readout circuits with single-to-differential PGA using intentional offset and two-step scaled-reference SAR ADC for CMOS image sensors

Abstract

High dynamic range (DR) readout circuits with an intentional offset fully differential output correlated double sampling (CDS) programmable gain amplifier (PGA) and a 14-bit differential input range two-step scaled-reference successive approximation register (SAR) analog digital converter (ADC) are proposed in this paper. The PGA is designed to add an intentional offset to prevent the circuits from saturation in the dark–light environment and convert single-ended and unipolar sensor voltages into a differential and bipolar form for a following-up fully differential input range ADC to improve DR of the readout circuits. The SAR ADC composes 7-bit complementary capacitor array to realize 14-bit differential resolution. Scaled reference buffers with self-calibration operation is presented to work in with the SAR ADC. The PGA and ADC work in pipeline mode to increase the frame rate. The 14-bit readout circuits operating at 600 kSps are integrated in a CMOS image sensor (CIS) with 160 × 190 pixel number, 3000 frame/s (fps) and 25 μm × 25 μm pixel pitch for remote sensing. It is verified using 180 nm CMOS process. The measurement results show that the SNR and SNDR of the prototype ADC is 73.90 and 73.01 dB respectively. The referred input noise of the readout circuits is 117 μVrms. A single column readout circuit consumes 2.48 mW under 3.3 V supply voltage. The figure of merit (FoM) of the CIS is 198 μV × nJ.