Abstract
In this work, design technique and analysis of low-energy consumption successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. A dual capacitor array (CA) generates a digital-to-analogue reference voltage with increased accuracy. The CA supports multiple parallel operations to enhance conversion speed. Unit sized capacitors in CAs are few in number and present good capacitance density, thereby providing area efficiency and ease of routeing. A 9-bit SAR ADC using the proposed dual CA, implemented in a 90 nm CMOS process, has a small core area footprint of 0.00371 mm 2 . At a 1 V supply and 100 kS/s, the ADC achieves a signal-to-noise and distortion ratio of 53.55 dB and consumes 0.47 μW, resulting in a figure-of-merit of 14.5 fJ/conversion step.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.