Abstract

This paper presents a self-biased current-reuse low noise amplifier (LNA) using self-cascode transistors, to obtain higher gains at lower supply voltages. Quasi-differential configuration is used to achieve high linearity and common-mode rejection. Complementary post-distortion (CPD) technique is also proposed to minimize the third order non-linearity of the LNA. The proposed LNA implemented in 65nm UMC low leakage CMOS process technology with a 1.2V supply occupies a core area of 0.01mm2. The LNA without CPD has low NF (1.42–1.65dB) and good gain (18.4–20.6dB) at low power dissipation (1.98mW) in the 3.25–4.5 GHz frequency band. The average 2nd order input intercept point (IIP2), 3rd order input intercept point (IIP3), and 1dB compression point (P 1dB ) are (+48.53dBm, +0.172dBm, −14.53dBm). Monte Carlo simulations of IIP3 are within ±2σ. The LNA with CPD achieves significant improvement in the average P 1dB (+3.72dBm) and average IIP3 (+3.18dBm) at the cost of higher power dissipation (+0.6mW).

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