Abstract
In this paper, a novel 120V multiple RESURF lateral double-diffused MOS (LDMOS) transistor with shallow trench isolation (STI) structure in low side is developed and successfully simulated. The proposed multiple RESURF LDMOS is able to achieve better ESOA performance while maintaining a benchmark specific on-resistance with breakdown voltage over 120 Volts. The key feature of this novel device is linear p-top rings which are located in the n-drift region. Optimization of p-top mask design and n-drift region concentration is performed in order to achieve the lowest on-resistance possible with the desired breakdown voltage.
Highlights
lateral double-diffused MOS (LDMOS) transistors are widely used in smart power technologies; Applications are mainly in display drivers, power switching, digital audio and power management devices etc
LDMOS can be integrated into a CMOS or a BiCMOS process which facilitates the fabrication of control, logic and power switches on a single chip [1,2]
In order to broaden the applicability of n-channel lateral DMOS transistor (NLDMOS), it is necessary to enhance the electrical performances, such as breakdown voltage, low on-state resistance, and high current driving capability [5]
Summary
LDMOS transistors are widely used in smart power technologies; Applications are mainly in display drivers, power switching, digital audio and power management devices etc. The focus is to optimize and improve the LDMOS device design to obtain power switches with very low specific on-state resistance (Rsp) while maintaining the high switching speed. LDMOS can be integrated into a CMOS or a BiCMOS process which facilitates the fabrication of control, logic and power switches on a single chip [1,2] For this voltage range, an optimized LDMOS is much more efficient in terms of on-state voltage and switching losses compared to a power bipolar junction transistor (BJT) or other hybrid MOS bipolar devices [3]. The main purpose of this structure is to increase the optimum charge in the drift region without reducing breakdown voltage for obtaining high breakdown voltage and low specific on-state resistance requirements in conventional NLDMOS devices. Schematic view of new N-channel LDMOS Structure with side isolations (a) Front view and (b) Top view
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