Abstract
We present an R&D program to develop an ASIC that contains a 12-channel VCSEL (Vertical Cavity Surface Emitting Laser) array driver operating at 10 Gb/s per channel, yielding an aggregated bandwidth of 120 Gb/s. The design of the 10 Gb/s array driver ASIC is based on a prototype ASIC for driving a VCSEL array at 5 Gb/s. We will briefly describe the design of the 5 Gb/s ASIC that was fabricated in a 130 nm CMOS process. Two ASICs were irradiated with 800 MeV protons to a dose of 0.92×1015 1-MeV neq/cm2 and remain operational. For the 10 Gb/s VCSEL array driver ASIC, we have submitted for fabrication a four-channel test chip using a 65 nm CMOS process. The circuit design together with the result from a simulation of the extracted layout with parasitic capacitance and inductance will be presented.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
