Abstract
This article presents a power amplifiers (PA) driver IC which has a parallel combined structure with a dual bias network.Each PA cell for parallel combination has an optimized bias to achieve both lower current consumption and IM3 cancellation at the same time, so that the overall PA driver IC has an improved linearity with a low current consumption. An incomplete Wilkinson divider including an input matching capability was proposed. This was adopted to prevent a stability degradation which can be caused by a parallel combination. The proposed PA driver IC was designed. This was implemented using a 2-μm InGaP/GaAs heterojunction bipolar transistor (HBT) to have an output power of 1 Watt. The quiescent currents for the upper and lower PA cells were optimized to have the best compromised performances with quiescent current levels of 100 and 150 mA, respectively. By the implemented PA driver IC, a gain of 17.25 dB and a high power-added efficiency of 54.15% at a P1dB of 31 dBm were achieved at a center frequency of 900 MHz. For a two-tone signal having a tone-spacing of 1 MHz, it also exhibited a high output IP3 of 54.28 dBm at an output power level of 20 dBm. The average output power was 22.36 dBm to which the IMD3 level should be lower than −60 dBc. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:1680–1683, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27639
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