Abstract
For pt. IV see ibid., vol.SC14, no.2, p.268 (1979). An n-channel single-level polysilicon, 25 nm gate-oxide technology, using electron-beam lithography with a minimum feature size of 1 /spl mu/m, has been implemented for MOSFET logic applications. The six-mask process employs semirecessed oxide isolation and makes extensive use of ion implantation, resist liftoff techniques, and reactive ion etching. A description of the process is given, with particular emphasis on topographical considerations. Implementation of a field etchback after source/drain implant to eliminate a low thick-oxide parasitic-device threshold is also discussed.
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