1- and 80-MS/s SAR ADCs in 40-nm CMOS With End-to-End Compilation

Abstract

This paper presents an end-to-end successive-approximation-register (SAR) analog-to-digital converter (ADC) compiler that generates design solutions from top-level specification to GDSII layout with a short turnaround time of 5 hours. Two prototype SAR ADCs operating at 1MS/s and 80MS/s are compiled in 40nm CMOS. Measurement results demonstrate a wide conversion range, presenting both analog and technology-limited performances. The compiler requires minimum manual involvement and can significantly boost design efficiency for performance retargeting, technology migrations, and agile development of IP blocks.